One example of a conventional pulse stretching circuit is illustrated in FIG. 1. A pulse stretching circuit 100 is constituted by a pulse delay circuit 110 and an OR gate 120. The pulse delay circuit 110 includes two or more even number of serially-connected inverters, that is, NOT (negative) circuits. The OR gate 120 includes a 2-input NOR (non-disjunction) circuit and an inverter connected in series thereto. The pulse delay circuit 110 generates a delay pulse signal b from an input pulse signal a, and the OR gate 120 generates a logical sum of the input pulse signal a and the delay pulse signal b to generate an output pulse signal c having a stretched pulse width.
FIG. 2 illustrates a waveform diagram of each of the pulse signals a, b and c. In (A), the delay pulse signal b (a displaced portion) is generated at a timing that does not exceed a pulse width of the input pulse signal a (a width of its displaced portion), thereby generating the output pulse signal c (a displaced portion) having a pulse width stretched due to overlap of the displaced portion of the delay pulse signal b with the displaced portion of the input pulse signal a (normal operation waveform). On the other hand, in (B), the delay pulse signal b is generated at a timing which exceeds the pulse width of the input pulse signal a, namely, in an extremely delayed fashion, thereby generating the output pulse signal c having a glitch (two displaced portions) because the displaced portion of the input pulse signal a and the displaced portion of the delay pulse signal b do not overlap with each other (abnormal operation waveform). When a pulse waveform with a glitch is used, malfunctions of a circuit are caused, and therefore, a pulse stretching circuit which does not cause glitches is required.
As a method for realizing a pulse stretching circuit which does not cause glitches, there have been known a circuit 300 having such a structure that normal pulse stretching circuits 100 are connected in series at multiple stages as illustrated in FIG. 3 and a circuit 400 having such a structure that pulse stretching circuits 100′ are hierarchically used at portions for pulse delay circuits 110 as illustrated in FIG. 4. In either case, a pulse delay circuit should be divided into a plurality of circuits and each of the divided circuits requires an OR gate, thereby making a circuit scale large. A large circuit scale increases a manufacture cost of a circuit and increases power consumption, which becomes a problem.
Japanese Unexamined Patent Publication No. 9-83313 discloses a pulse-width adjustment circuit in which chopper circuits, each including an inverter string for delaying an input pulse and an OR gate circuit for receiving the input pulse and a delay pulse from the inverter string, are connected in cascade at two stages.
Japanese Unexamined Patent Publication No. 11-136103 discloses a pulse stretching circuit in which circuits, each including a delay element for delaying an input signal and an AND element for receiving the input signal and a delay signal from the delay element, are connected in series at multiple stages.
Japanese Unexamined Patent Publication No. 2001-223569 discloses a pulse stretching circuit in which a plurality of serially-connected buffers are connected in series with each other at three stages via AND gates each provided between respective stages, and an OR operation is performed on an input signal of the endmost input port of the three stages, an output signal of each stage, and an output signal of the endmost output port of the three stages so as to stretch a pulse width.
Japanese Unexamined Patent Publication No. 7-93975 discloses that a plurality of delay circuits are connected in series with each other, and an OR operation is performed on an input pulse signal and output pulse signals of the respective delay circuits so as to synthesize and stretch a pulse signal.